Active matrix display screen permitting the display of gray levels

ABSTRACT

A single signal is produced, which includes a pedestal and a ramp. This signal is supplied to a column control circuit which transmits the voltage to each column for a time which can assume a number of discrete values between t 1 , the pedestal duration, and T L , the addressing time of one row. For t 1 , the black level is obtained, for T L  the white level and between them, various gray levels.

BACKGROUND OF THE INVENTION

The present invention relates to an active matrix display screenpermitting the display of gray levels.

An active matrix display screen is diagrammatically shown in FIG. 1 andcomprises a first wall 10 on which are deposited a matrix of N by Pelectrodes 12 forming first capacitor plates or coating, N addressingrows 14 and P addressing column 16, NP control transistors 18 eachhaving a drain, a gate and a source, the drain of each transistor beingconnected to the plate 12 of one of the capacitors, the source to one ofthe columns 16 and the gate to one of the rows 14; a second wall 20 onwhich is deposited a counterelectrode 22 forming the second plate orcoating of the capacitors; a first row control circuit 30 able tosuccessively apply to the N rows 14 a voltage V_(L) able to make thetransistors of each row conductive for a time T_(L), the control of theN rows constituting a frame of duration Tr=NT_(L) ; a second controlcircuit 32 able to apply to the counterelectrode 22 a voltage Vcesuccessively assuming two values, a value 0 and a value Vc, the voltageVce passing from one to the other of these values, either after eachframe, or after each row; and a third column control circuit 34 able toapply a set of P voltages to the columns 16 throughout the control timeof a row.

FIG. 2 shows a detail of a display point. It is possible to see anaddressing row Li, An addressing column Cj, a transistor Tij having agate G, a source S and a drain D and finally a conductor block Cij.Source S is connected to column Cj, a gate G to row Li and drain D toblock Cij.

For controlling a display point corresponding to plate Cij, transistorTij is opened for a time T_(L). A potential difference between column Cjlinked with source S of Tij and counterelectrode 22 brings about acharge flow into the transistor channel. These charges are stored ondrain D, i.e. finally on plate Cij and, symmetrically, on thecounterelectrode. Following the row addressing time, transistor Tij ismade non-conductive. The charge Qij stored in the capacitor remainsthere and a voltage Vij is permanently applied to the display material,i.e. to the liquid crystal. This voltage is equal to Qij/Kij, if Kijdesignates the capacitance of the display point.

If it is wished to display a gray level, it is necessary to give thisratio a value between 0 and a value Vmax corresponding to a saturatedstate (white).

Two solutions are known in the prior art for displaying such graylevels. The first is illustrated in FIG. 3. In the latter and in thefollowing drawings, the time is broken up into row addressing intervalsof duration T_(L) and, for simplification purposes, it is assumed thatthe screen contains 5 rows L₁, L₂. . . L₅. The scan of these 5 rowsconstitutes a first frame and the scan of the 5 following rows a secondframe.

Part a of FIG. 3 shows the voltage Vcj applied to a random volume ofrank j. This voltage is shown in broken line form. It is also possibleto see the voltage VCe applied to the counterelectrode (in continuousline form). The latter is 0 for the first frame and then equal to Vmaxduring the second. The voltage applied to a column varies between 0 andVmax, in accordance with a voltage scale. The resulting voltage appliedto the display point located on column j is equal to the differenceVCj-VCe, which corresponds to the hatched area. It can be seen that saidvoltage has a mean value 0, because of the alternation at each frame (toprevent charge accumulation phenomena which might damage the liquidcrystal).

With respect to the voltage Vij appearing on a given display point,e.g., on the second row and the jth column, it varies as shown in partb. During the interval when the second line is addressed, the voltageincreases up to a value Vgr and then when the line is no longeraddressed, the voltage remains at this value.

The advantage of this method is that by using relatively conductivetransistors, at the end of the row addressing time, voltage Vij reacheslevel Vgr corresponding to the gray to be displayed and this voltage isnot dependent on the value of the transistor drain current. The graylevels will then be reproduced on the screen with the same brightnesslevel for all points.

However, the disadvantage of this method is that it makes it necessaryto produce a large number of voltages Vgr (the same number as graylevels are desired), which makes the control circuit very complex.

There is another gray display control method, which is illustrated inFIG. 4. In part a, it is possible to see in continuous line form, thevoltage Vce applied to the counterelectrode and in broken line form thevoltage VCj applied to a column of rank j during the various row controlintervals. It can be seen that the display time of a point is subdividedinto two intervals and during the first, of duration t₁, the column isbrought to the same potential as the counter electrode, whereas duringthe second it is brought to a voltage Vmax. Moreover, use is made oflimited conduction transistors, so that the voltage Vij (shown in partb) does not reach the maximum value Vmax, if interval t₂ is below thetotal addressing interval of a row T_(L).

The advantage of the second solution compared with the first, is that itonly requires two voltage levels for the control of the rows, namely 0and Vmax. Its disadvantage is that the voltage finally reached isdependent on the drain current of the controlled transistor. However,this current is in fact difficult to control for technological reasons,so that the reproduction on a screen of the same brightness at severalpoints and for a same gray level is difficult to obtain.

SUMMARY OF THE INVENTION

The object of the present invention is to make the visual effectindependent or only slightly dependent on dispersions of characteristicsof the transistors, whilst leading to very simple control circuits.Therefore the invention recommends the use of a circuit which supplies asingle voltage having a pedestal and a ramp (and no longer a voltagesscale as in the first prior art method, or two voltage scales as in thesecond), said voltage being applied to column control circuits, whichtransmit it for a time which can assume various discrete values. Thesecontrol circuits can be very simply obtained, e.g. by means of a singletransistor. With the solution according to the invention, the levelsdisplayed are not sensitive to the dispersions of the characteristics ofthe transistors, because the voltage applied to the display material ismade independent of the drain current of the transistors. This propertyis of interest particularly for large panels, because it permits adispersion of the characteristics of the transistors between e.g. thecenter of the screen and its periphery. Therefore it increases themanufacturing tolerances of large area screens.

More specifically the present invention relates to a display screen ofthe type described hereinbefore in connection with FIG. 1 and which ischaracterized in that the third column control circuit comprises acircuit supplying a voltage Vcb which, for a duration t₁, has a valueequal to the voltage Vce applied to the counterelectrode and for aduration t₂ a ramp-like voltage varying linearly between said voltageVce and a voltage differing from Vce by a quantity Vc, the totalduration t₁ +t₂ of the voltage Vcb being equal to the control durationT_(L) of one row; column control circuits connected between said circuitand each column and which transmit to each column said voltage Scb for atime which can assume a series of discrete values between t₁, in whichcase a black display is obtained, and T_(L), in which case a whitedisplay is obtained, each intermediate discrete value between t₁ andT_(L) corresponding to a gray display.

Preferably, the control circuits of the columns connected between thecircuit producing Vcb and each column are constituted by P transistorshaving a source connected to the circuits applying the voltage Vcb, Adrain connected to one of the P columns and a gate connected to a meansable to supply a transistor opening control voltage for a time which isa function of the gray level to be displayed.

Preferably, the means able to supply an opening control voltage for theP transistors is constituted by P shift registers of n cells each, thefirst cell of each register being connected to the gate of one of thetransistors, one register containing n bits, whereof the first is alwaysequal to 1 and the following ones are equal to 0 or to 1, all these nbits characterising a gray level. These registers are controlled by acommon clock of period t₁, which controls the shift of the bits in eachregister. Duration t₁ is such that nt₁ is equal to the total controltime T_(L) of a row.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in greater detail hereinafter relative tonon-limitative embodiments and with reference to the attached drawings,wherein show:

FIG. 1, already described, a prior art screen.

FIG. 2, already described, a detail of such a screen.

FIG. 3, already described, a first known variant for the control of graylevels.

FIG. 4, already described, a second known variant for the control ofgray levels.

FIG. 5, an example for the control of the transistors of the same row.

FIG. 6, the shape of the single voltage produced according to theinvention.

FIG. 7, the voltages applied in order to obtain a white level.

FIG. 8, the voltage applied to the display point and the state of thecontrol circuits in the case of a white control.

FIG. 9, the voltage applied in the case of a black display.

FIG. 10, the evolution of the voltage applied to a display point for agiven gray level and the state of the corresponding control circuits.

FIG. 11, an example of writing a white level followed by the writing ofa black level.

FIG. 12, an embodiment of the column control circuits according to theinvention using transistors.

FIG. 13, the ramp-shaped voltage applied to the sources of all thetransistors and the clock pulses controlling the shift registers.

FIG. 14, a variant corresponding to the case of an alternation aftereach row and no longer after each frame.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Part a of FIG. 5 shows the voltage VG applied to a particular row (e.g.the third row) i.e. definitively the voltage applied to the gates oftransistors connected to said row. This voltage is either equal to VGb,which corresponds to an off state of the transistor, or to VGbcorresponding to an on state of said transistor. In part b of FIG. 5,the on state is designated EP and the off state EB. The vertical arrowsshow the passage of the transistors from one state to the other. It ispointed out that this addressing mode is not unique to the invention,but is already used in the prior art.

However, what is specific to the invention is the single voltageproduced for controlling the display. This single voltage is shown inFIG. 6. The two shapes a and b correspond to the two cases of an evenframe and an uneven frame, on alternating the voltage of thecounterelectrode Vce after each frame, or by a even row and an unevenrow on alternating Vce after each row. The single voltage Vcb is formedfrom a pedestal of duration t₁ having a value equal to the voltage ofthe counterelectrode Vce (i.e. 0 in the case a and Vc in case b) and alinear ramp of duration t₂, which passes the voltage from the precedingvalue to a value differing from Vce by a quantity Vc (i.e. which reachesVc in case a and 0 in case b). The total duration t₁ +t₂ is equal to thecontrol duration T_(L) of a row.

In FIGS. 7 to 11, it is assumed that the polarity alternation takesplace after each frame. FIG. 14 illustrates the case where thealternation takes place after each row.

FIG. 7 shows in part a the single voltage Vcb during various row scans(it still being assumed that a frame is formed from five row scans) andin part b the counter -electrode voltage Vce and its alternation at eachframe. Thus, the voltage ramp Vcb has a positive slope for one frame(which corresponds to the signal of FIG. 6a) and a negative slope forthe following frame (which corresponds to the signal of FIG. 6b).

On now considering a particular column, it is necessary to determine theinterval during which said single voltage will be applied to the column.This time is determined by control circuits which, as will be shownhereinafter, can be transistors brought into the on or off state. InFIGS. 8 to 11, these states are represented in part b by an on state EPand an off state EB.

Interest is attached in FIG. 8 to a point located on the third row andon a random column, it being assumed that the white is to be displayedon this point. The column control circuit must therefore be on for thecomplete duration T_(L). For the pedestal of duration t₁, the controlcircuit is on, the capacitor discharges and the voltage drops to 0. Thenthe control circuit remains on, the voltage follows the ramp and reaches+Vc or -Vc and so on, so that a white display is obtained.

FIG. 9 corresponds to the display of a black point. The control circuitis only conductive or on for the time interval t₁, i.e. when Vcb isequal to Vce. In other words, no potential difference is applied betweenthe capacitor plates at the intersection of the considered column andthe third row.

FIG. 10 illustrates an intermediate state, where it is wished to displaya gray level. In this case, the column control circuit is open not onlyfor the pedestal of duration t₁ (but also for a time t₂ corresponding tothe voltage ramp). This value t₂ is still limited and does not reach thevalue T_(L) -t₁, as in the white display case. Thus, the voltage appliedstarts by dropping to a 0 value (which corresponds to the pedestal t₁)and then follows part of the ramp of signal Vcb (corresponding tointerval t₂). This intermediate voltage level reached corresponds to agray level.

FIG. 11 shows how one passes from a white display to a black display. Onthe first frame, the column control circuit is on for the complete rowaddressing period. Thus, at the end of row scanning, the voltage appliedreaches the voltage Vc corresponding to the white level. At thefollowing frame, the control circuit is on for the duration t₁, whichcorresponds to the pedestal where the voltage applied is 0 and whichbrings about the discharge of the capacitor. However, this circuit isoff or non-conductive immediately thereafter, which prevents the voltagefrom leaving the value 0, so that the displayed point remains at theblack level.

FIG. 12 shows an embodiment of the construction of the column controlcircuits, which are constituted by transistors TR1, TR2....TRj having asource connected to a circuit 40, which supplies the single voltage, asillustrated in FIG. 6, as well as a drain connected to a column. Forcontrolling the opening and closing of these transistors, use can bemade of shift registers SR1, SR2. ...SRj, whereof the first cell isconnected to the gate of each of the transistors TR1, TR2....TRj. Allthese registers are controlled by a single clock 42, which emitsperiodic pulses separated by a time interval equal to t₁. FIG. 13 showsthe voltage supplied by the circuit 40 (a) and the clock pulses (b).

In the illustrated case, the shift registers comprise 4 cells, becausethe duration T_(L) is equal to 4t₁. The cells are loaded by 1 or by 0,as a function of the display to be performed. The first cell iscertainly loaded by a 1 . The transistors TRj are always on for time t₁.For displaying a white level, the register is loaded with the sequence1111. The corresponding transistor is open over the entire pedestal andthe ramp following the 4 clock pulses (which corresponds to the caseillustrated in FIG. 8). For displaying a light gray level, the registeris loaded with the sequence 0111, which corresponds to an interval t₂open for 2t₁ (which corresponds to the example illustrated in FIG. 10).For a dark gray, use will be made of the sequence 0011 and for the blackthe sequence 0001. Thus, for the latter case, the transistor will onlybe opened for the pedestal t₁ (which corresponds to the exampleillustrated in FIG. 9).

Circuit 44 is used for loading the shift registers as a function of thedisplay to be performed on the various columns. Each value is coded inaccordance with one of the aforementioned 4 sequences and the loadingtakes place at each row control.

Circuit 40 supplying the single signal in FIG. 1 can comprise atriangular signal generator dependent on the row frequency of the syncsignal (video).

In the embodiments described, the polarity alternation of the controlvoltage takes place after each frame. This alternation can also takeplace after each row. This is illustrated in FIG. 14, where part a showsthe signal applied to the input of all the column control circuits andpart b the voltage applied to the counterelectrode.

What is claimed is:
 1. An active matrix display screen comprising afirst wall on which are deposited a matrix of N by P electrodes formingthe first plates of capacitors, N addressing columns and P addressingrows, NP control transistors each having a drain (D), a gate (G) and asource (S), the drain (D) of each transistor being connected to theplate of one of the capacitors, the source to one of the columns and thegate to one of the rows; a second wall on which is deposited acounterelectrode forming the second plate of the capacitors; a firstcontrol circuit able to successively apply to the N rows a voltage Veable to make the transistors of each row on for a time T_(L), thecontrol of the N rows constituting a frame of duration Tr=NT_(L) ; asecond control circuit able to apply to the counterelectrode a voltageVce successively assuming two values, namely a value 0 and and a valueVc, the voltage Vce passing from one to the other of these values eitherfollowing each frame, or following each row; and a third control circuitable to apply to the P columns for the entire control time of a row, aset of P voltages, said screen being characterized in that the thirdcontrol circuit comprises a circuit supplying a voltage Vcb having apedestal of duration t₁ of value equal to the voltage Vce applied to thecounterelectrode and for a duration t₂ a ramp-like voltage passinglinearly from said voltage Vce to a voltage differing from Vce by aquantity Vc, the total duration t₁ +t₂ of the voltage Vcb being equal tothe control time T_(L) of a row; and secondary column control circuitsconnected between said third control circuit and each column and whichtransmit to each column said voltage Vcb for a time which can assume aseries of discrete values between t₁, in which case a black display isobtained, and T_(L) in which case a white display is obtained, eachintermediate discrete value between t₁ and T_(L) corresponding to a graydisplay.
 2. A display screen according to claim 1, wherein the thirdcontrol circuit is constituted by P transistors having a sourceconnected to the circuit supplying the voltage Vcb, a drain connected toone of the P columns and an gate connected to a operating circuit ableto supply a voltage for controlling the turning on of the transistor fora time which is a function of the gray level to be displayed.
 3. Adisplay screen according to claim 2 wherein said operating circuit isable to supply a voltage for controlling the turning on of P transistorsis constituted by P shift registers having n cells each, the first cellof each register being connected to the gate of one of the transistor,each register containing n bits, whereof the first is always equal to 1and the following bits to 0 or 1, all these n bits characterizing a graylevel, said registers being controlled by a common clock of period t₁,which is equal to said pedestal duration and which control the shift ofthe bits into each register, the duration t₁ being such that nt₁ isequal to the total row control duration T_(L).